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OKI Semiconductor ML9044A-xxA/xxB
DOT MATRIX LCD CONTROLLER DRIVER
PEDL9044A-04
Issue Date: Apr. 8, 2002
Preliminary
GENERAL DESCRIPTION
The ML9044A used in combination with an 8-bit or 4-bit microcontroller controls the operation of a character type dot matrix LCD.
FEATURES
* * * * * * * * * * * * * * * * * Easy interfacing with 8-bit or 4-bit microcontroller Switchable between serial and parallel interfaces Dot-matrix LCD controller/driver for a small (5 x 7 dots) or large (5 x 10 dots) font Built-in circuit allowing automatic resetting at power-on Built-in 17 common signal drivers and 120 segment signal drivers Built-in character generation ROM capable of generating 160 small characters (5 x 7 dots) or 32 large characters (5 x 10 dots) Creation of character patterns by programming: up to 8 small character patterns (5 x 8 dots) or up to 4 large character patterns (5 x 11 dots) Built-in RC oscillation circuit using external or internal resistors Program-selectable duties: 1/9 duty (1 line: 5 x 7 dots + cursor + arbitrator), 1/12 duty (1 line: 5 x 10 dots + cursor + arbitrator), or 1/17 duty (2 lines: 5 x 7 dots + cursor + arbitrator) Built-in bias dividing resistors to drive the LCD Bi-directional transfer of segment outputs Bi-directional transfer of common outputs 120-dot arbitrator display Line display shifting Built-in contrast control circuit Built-in voltage multiplier circuit Gold Bump Chip With dummy bumps on both sides of the chip: ML9044A-xxA CVWA Without dummy bumps on both sides of the chip: ML9044A-xxB CVWA *xx indicates a character generator ROM code number. *51A and 51B indicate general character generator ROM code numbers.
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VDD GND
OKI Semiconductor
OSC1 OSCR OSC2 7 Common signal driver COM1 COM17 Cursor blink controller 17-bit shift register 8 Instruction decoder (ID) Parallelserial converter Character generator RAM (CG RAM) 5 5 8 8 8 Character generator ROM (CG ROM)
BLOCK DIAGRAM
Timing generator
8
Instruction register (IR)
RS1 RS0 R/W E CS S/P SHT SI SO
I/O buffer
SEG1
4 Address counter (ADC) Display data RAM (DD RAM) 5
8
DB0 to DB3 DB4 to DB7
120-bit latch
4
Data register (DR)
Segment Signal - driver
120-bit shift register
T1 T2 T3
Test circuit
8
V1 V2 V3A V3B V4 V5 Arbitrator RAM (AB RAM)
Voltage multiplier circuit
LCD bias voltage dividing circuit
Expansion Expansion 8 instruction decoder instruction (ED) register (ER)
Busy flag (BF)
5
SEG120
Contrast control circuit BE
V5IN
CSR SSR
PEDL9044A-04
ML9044A-xxA/xxB
VCC VC VIN
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I/O CIRCUITS
VDD P
P VDD
VDD
VDD P
N
N
N
Applied to pins SSR, CSR, S/P, and BE
Applied to pins T1, T2, and T3
Applied to pins R/W, RS1, and RS0
: "0" At serial I/F At parallel I/F : "1" Applied to pin E Applied to pin SI
At serial I/F At parallel I/F
: "1" (CS = "0") : "0" (CS = "1") : "0"
At serial I/F Applied to pin SHT At parallel I/F
: "1" (CS = "1") : "0" (CS = "0") : "1"
: "0" At serial I/F At parallel I/F : "1" Applied to pin CS
VDD
VDD
P
P VDD N P
N Output Enable signal Applied to pins DB0 to DB7
VDD
VDD
P
P N Output Enable signal Applied to pin SO
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PIN DESCRIPTIONS
Symbol R/W
Description The input pin with a pull-up resistor to select Read ("H") or Write ("L") in the Parallel I/F Mode. This pin should be open in the Serial l/F Mode. The input pins with a pull-up resistor to select a register in the Parallel l/F Mode. RS1 RS0 H L L Name of register Data register Instruction register Expansion Instruction register
RS0, RS1
H H L
This pin should be open in the Serial I/F Mode. E The input pin for data input/output between the CPU and the ML9044A and for activating instructions in the Parallel l/F Mode. This pin should be open in the Serial l/F Mode. The input/output pins to transfer data of lower-order 4 bits between the CPU and the ML9044A in the Parallel l/F Mode. The pins are not used for the 4-bit interface and serial interface. Each pin is equipped with a pull-up resistor, so this pin should be open when not used. The input/output pins to transfer data of upper 4 bits between the CPU and the ML9044A in the Parallel l/F Mode. The pins are not used for the serial interface. Each pin is equipped with a pull-up resistor, so this pin should be open in the Serial I/F Mode when not used. The clock oscillation pins required for LCD drive signals and the operation of the ML9044A by instructions sent from the CPU. OSC1 OSC2 OSCR To input external clock, the OSC1 pin should be used. The OSCR and the OSC2 pins should be open. To start oscillation with an external resistor, the resistor should be connected between the OSC1 and OSC2 pins. The OSCR pin should be open. To start oscillation with an internal resistor, the OSC2 and OSCR pins should be short-circuited outside the ML9044A. The OSC1 pin should be open. The LCD common signal output pins. COM1 to COM17 SEG1 to SEG120 For 1/9 duty, non-selectable voltage waveforms are output via COM10 to COM17. For 1/12 duty, non-selectable voltage waveforms are output via COM13 to COM17. The LCD segment signal output pins.
DB0 to DB3
DB4 to DB7
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Symbol CSR
Description The input pin to select the transfer direction of the common signal output data. At 1/n duty, data is transferred from COM1 to COMn when "L" is applied to this pin and transferred from COMn to COM1 when "H" is applied to this pin. The input pin to select the transfer direction of the segment signal output data. "L": Data transfer from SEG1 to SEG120 "H": Data transfer from SEG120 to SEG1 The pins to output bias voltages to the LCD.
SSR
V1 , V2, V3A, V3B, V4
For 1/4 bias : The V2 and V3B pins are shorted. For 1/5 bias : The V3A and V3B pins are shorted. The input pin to enable or disable the voltage multiplier circuit. "L" disables the voltage multiplier circuit. "H" enables the voltage multiplier circuit.
BE
The voltage multiplier circuit doubles the input voltage between VDD and VIN and the multiplied voltage referenced to VDD is output to the V5IN pin. The voltage multiplier circuit can be used only when generating a level lower than GND. The pin to input voltage to the voltage multiplier. The pins to supply the LCD drive voltage. The LCD drive voltage is supplied to the V5 pin when the voltage multiplier is not used (BE = "0") and the internal contrast adjusting circuit is also not used. At this time, the V5IN pin should be open.
VIN
V5, V5IN
The LCD drive voltage is supplied to the V5IN pin when the voltage multiplier is not used (BE = "0") but the internal contrast adjusting circuit is used. At this time, the V5 pin should be open. When the voltage multiplier is used (BE = "1"), the V5 pin should be open (the multiplied voltage is output to the V5IN pin). In this case, the internal contrast adjusting circuit must be used. Capacitors for the voltage multiplier should be connected between the VDD pin and the V5IN pin.
VC VCC
The pin to connect the positive pin of the capacitor for the voltage multiplier. Leave the pin open when the voltage multiplier circuit is not used. The pin to connect the negative pin of the capacitor used for the voltage multiplier. Leave the pin open when the voltage multiplier circuit is not used.
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Symbol T 1, T 2, T 3 VDD GND S/P
Description The input pins for test circuits (normally open). Each of these pins is equipped with a pull-down resistor, so this pin should be left open. The power supply pin. The ground level input pin. The input pin to select the serial or parallel interface. "L" selects the parallel interface. "H" selects the serial interface. The pin to enable this IC in the serial l/F mode. "L" enables this IC. "H" disables this IC. This pin should be open in the parallel l/F mode. The pin to input shift clock in the serial l/F mode. Data inputting to the SI pin is carried out synchronizing with the rising edge of this clock signal. Data outputting from the SO pin is carried out synchronizing with the falling edge of this clock signal. This pin should be open in the parallel l/F mode. The pin to input DATA in the serial l/F mode. Data inputting to this pin is carried out synchronizing with the rising edge of the SHT signal. This pin should be open in the parallel l/F mode. The pin to output DATA in the serial l/F mode. Data inputting to this pin is carried out synchronizing with the falling edge of the SHT signal. This pin should be open in the parallel l/F mode. NC pin. Leave this pin open.
CS
SHT
Sl
SO
DUMMY
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ABSOLUTE MAXIMUM RATINGS
(GND = 0 V) Parameter Supply Voltage LCD Driving Voltage Symbol VDD V1, V2, V3, V4, V5 VI TSTG Condition Ta = 25C Ta = 25C Rating -0.3 to +6.5 VDD-7.5 to VDD+0.3 Unit V V Applicable pins VDD-GND V1, V4, V5, V5IN, V2, V3A, V3B R/W, E, SHT, CSR, S/P, SSR, Sl, RS0, RS1, BE, CS, T1 to T3, DB0 to DB7, VIN --
Input Voltage Storage Temperature
Ta = 25C --
-0.3 to VDD+0.3 -55 to +150
V C
RECOMMENDED OPERATING CONDITIONS
(GND = 0 V) Parameter Supply Voltage LCD Driving Voltage Voltage Multipler Operating Voltage Operating Temperature Symbol VDD VDD-V5 (See Note) VMUL Top Condition -- -- BE = "1" -- Range 2.7 to 5.5 3.3 to 7.0 2.7 to 3.5 -40 to +85 Unit V V V C Applicable pins VDD-GND VDD-V5 (V5IN) VDD-VIN --
Note: This voltage should be applied across VDD and V5. The following voltages are output to the V1, V2, V3A (V3B) and V4 pins: * 1/4 bias V1 = {VDD - (VDD - V5)/4} 0.15 V V2 = V3B = {VDD - (VDD - V5)/2} 0.15 V V4 = {VDD - 3 x (VDD - V5)/4 } 0.15 V * 1/5 bias V1 = {VDD - (VDD - V5)/5} 0.15 V V2 = {VDD - 2 x (VDD - V5)/5} 0.15 V V3A = V3B = {VDD - 3 x (VDD - V5)/5} 0.15 V V4 = {VDD - 4 x (VDD - V5)/5} 0.15 V The voltages at the V1, V2, V3A (V3B), V4 and V5 pins should satisfy VDD > V1 > V2 > V3A (V3B) > V4 > V5. (Higher Lower) * If the chip is attached on a substrate using COG technology, the chip tends to be susceptible to electrical characteristics of the chip due to trace resistance on the glass substrate. It is recommended to use the chip by confirming that it operates on the glass substrate properly. Trace resistance, especially, VDD and VSS trace resistance, between the chip on the LCD panel and the flexible cable should be designed as low as possible. Trace resistance that cannot be very well decreased, larger size of the LCD panel, or greater trace capacitance between the microcontroller and the ML9044A device can cause device malfunction. In order to avoid the device malfunction, power noise should be reduced by serial interfacing of the microcontroller and the ML9044A device. * Do not apply short-circuiting across output pins and across an output pin and an input/output pin or the power supply pin in the output mode.
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = -40 to +85C) Parameter "H" Input Voltage "L" Input Voltage "H" Output Voltage 1 "L" Output Voltage 1 "H" Output Voltage 2 "L" Output Voltage 2 Symbol VIH -- VIL VOH1 VOL1 VOH2 VOL2 VCH VCMH VCML VCL VSH SEG Voltage Drop VSMH VSML VSL Input Leakage Current | IIL | IOH = -0.1 mA IOL = +0.1 mA IOH = -13 A IOL = +13 A lOCH = -4 A lOCMH = 4 A VDD -V5 = 5 V Note 1 lOCML = 4 A lOCL = +4 A lOSH = -4 A lOSMH = 4 A VDD -V5 = 5 V Note 1 lOSML = 4 A lOSL = +4 A VDD = 5 V, VI = 5 V or 0 V VDD = 5 V, VI = GND Input Current 1 | II1 | VDD = 5 V, VI = VDD, Excluding current flowing through the pull-up resistor and the output driving MOS VDD = 5 V, VI = VDD Input Current 2 | II2 | VDD = 5 V, VI = GND, Excluding current flowing through the pull-down resistor VDD = 5 V Note 2 0 0.75VDD -- 0.9VDD -- VDD-0.3 V1-0.3 V4-0.3 V5 VDD-0.3 V2-0.3 V3-0.3 V5 -- 10 -- 15 -- -- 2.5 Rf = 180 k2% Note 3 175 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 25 -- 45 -- -- 4.0 270 0.2VDD -- 0.2VDD -- 0.1VDD VDD V1+0.3 V4+0.3 V5+0.3 VDD V2+0.3 V3+0.3 V5+0.3 1.0 61 2.0 105 2.0 1.2 6.0 400 A mA k T 1, T 2, T 3 A R/W, RS0, RS1, DB0 to DB7, SO A E, SSR, CSR, BE, SHT, S/P, CS, Sl V SEG1 to SEG120 V V Condition Min. 0.8VDD Typ. -- Max. VDD V Unit Applicable pin R/W, RS0, RS1, E, DB0 to DB7, SHT, S/P, Sl, CS, OSC1, SSR, CSR, BE DB0 to DB7, SO OSC2
COM Voltage Drop
V
COM1 to COM17
Supply Current LCD Bias Resistor Oscillation Frequency of External Resistor Rf Oscillation Frequency of Internal Resistor Rf External Clock Clock Input Frequency Input Clock Duty Input Clock Rise Time Input Clock Fall Time
lDD RLB fosc1 fosc2
VDD-GND VDD, V1, V2, V3A, V3B, V4, V5
kHz OSC1, OSC2 kHz OSC1, OSC2, OSCR
fin fduty frf fff
Note 4 OSC1: Open OSC2 and OSCR: Shortcircuited OSC2, OSCR: Open Input from OSC1 Note 5 Note 6 Note 6
140
270
480
125 45 -- --
-- 50 -- --
480 55 0.2 0.2
kHz % s s OSC1
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(GND = 0 V, VDD = 2.7 to 5.5 V, Ta = -40 to +85C) Parameter Voltage Multiplier Input Voltage Symbol VMUL Note 7 VDD = 2.7 V, VIN = 0 V f = 125 kHz Voltage Multiplier Output Voltage V5OUT A capacitor for the voltage multiplier =1 to 4.7 F No load BE = "H" VDD = 5 V, V5IN = -2 V, 1/5 bias, Contrast data: 1F, No load VLCD MAX Maximum and minimum LCD drive voltages when internal variable resistors are used. Note 8 VLCD MIN VDD = 5 V, V5IN = -2 V, 1/4 bias, Contrast data: 1F, No load VDD = 4.1 V, V5IN = 0 V, 1/5 bias, Contrast data: 1F, No load VDD = 3.9 V, V5IN = 0 V, 1/4 bias, Contrast data: 1F, No load VDD = 5 V, V5IN = -2 V, 1/5 bias, Contrast data: 00, No load VDD = 5 V, V5IN = -2 V, 1/4 bias, Contrast data: 00, No load VDD = 4.1 V, V5IN = 0 V, 1/5 bias, Contrast data: 00, No load VDD = 3.9 V, V5IN = 0 V, 1/4 bias, Contrast data: 00, No load Bias Voltage for Driving LCD VLCD1 VDD-V5 VLCD2 Note 9 1/4 bias 3.3 -- 7.0 1/5 bias 6.6 6.6 3.8 3.6 4.0 3.6 2.2 1.9 3.3 -- -- -- -- -- -- -- -- -- 1/4 bias 3.9 -- 1/5 bias 4.1 -- Condition Min. 2.7 Typ. -- Max. 3.5 (VDD-VIN) x2 V (VDD-VIN) x2 -- -- V -- -- VDD-V5 4.6 4.2 V 2.8 2.5 7.0 V V5 VDD-V5IN Unit V Applicable pins VDD-VIN
Note 1:
Applied to the voltage drop occurring between any of the VDD, V1, V4 and V5 pins and any of the common pins (COM1 to COM17) when the current of 4 A flows in or flows out at one common pin. Also applied to the voltage drop occurring between any of the VDD, V2, V3A (V3B) and V5 pins and any of the segment pins (SEG1 to SEG120) when the current of 4 A flows in or flows out at one common pin. The current of 4 A flows out when the output level is VDD or flows in when the output level is V5.
Note 2:
Applied to the current flowing into the VDD pin when the external clock (fOSC2 = fin = 270 kHz) is fed to the internal Rf oscillation or OSC1 under the following conditions: VDD = 5 V GND = V5 = 0 V, V1, V2, V3A (V3B) and V4: Open E, SSR, CSR, and BE: "L" (fixed) Other input pins: "L" or "H" (fixed) Other output pins: No load
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Note 3:
Note 4:
OSC1 OSC1 OSCR OSC2 Rf = 180 k2% OSCR
OSC2
The wire between OSC1 and Rf and the wire between OSC2 and Rf should be as short as possible. Keep OSCR open.
The wire between OSC2 and OSCR should be as short as possible. Keep OSC1 open.
Note 5:
tHW tLW
VDD 2 fIN waveform
VDD 2
VDD 2
Applied to the pulses entering from the OSC1 pin fduty = tHW/(tHW + tLW) x100 (%)
Note 6:
0.8VDD 0.2VDD
0.8VDD 0.2VDD
trf
tff
Applied to the pulses entering from the OSC1 pin
Note 7:
The maximum value of the voltage multiplier input voltage should be set at 3.5 V, and the minimum value of the voltage multiplier input voltage should be set so that the voltage multiplier output voltage meets the specification for the bias voltage for driving LCD after contrast adjustment. If using the built-in contrast control circuit, control the circuit so that the voltage of VDD-V5 is the minimum value of the bias voltage for driving LCD or higher. For 1/4 bias, V2 and V3B pins are short-circuited. V3A pin is open. For 1/5 bias, V3A and V3B pins are short-circuited. V2 pin is open.
Note 8:
Note 9:
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Switching Characteristics (The following ratings are subject to change after ES evaluation.) * Parallel Interface Mode The timing for the input from the CPU (see 1) and the timing for the output to the CPU (see 2) are as shown below: 1) WRITE MODE (Timing for input from the CPU)
(VDD = 2.7 to 5.5 V, Ta = -40 to +85C) Parameter R/W, RS0, RS1 Setup Time E Pulse Width R/W, RS0, RS1 Hold Time E Rise Time E Fall Time E Pulse Width E Cycle Time DB0 to DB7 Input Data Hold Time DB0 to DB7 Input Data Setup Time Symbol tB tW tA tr tf tL tC tI tH Min. 40 450 10 -- -- 430 1000 195 10 Typ. -- -- -- -- -- -- -- -- -- Max. -- -- -- 25 25 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns
RS1, RS0
VIH VIL
VIH VIL
R/W
VIL tB tL tr VIH VIL tI tW tf VIH VIL tH Input Data
VIL tA
E
VIL
DB0 to DB7 tC
VIH VIL
VIH VIL
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2) READ MODE (Timing for output to the CPU)
(VDD = 2.7 to 5.5 V, Ta = -40 to +85C) Parameter R/W, RS1, RS0 Setup Time E Pulse Width R/W, RS1, RS0 Hold Time E Rise Time E Fall Time E Pulse Width E Cycle Time DB0 to DB7 Output Data Delay Time DB0 to DB7 Output Data Hold Time Symbol tB tW tA tr tf tL tC tD tO Min. 40 450 10 -- -- 430 1000 -- 20 Typ. -- -- -- -- -- -- -- -- -- Max. -- -- -- 25 25 -- -- 350 -- Unit ns ns ns ns ns ns ns ns ns
Note: A load capacitance of each of DB0 to DB7 must be 50 pF or less.
RS1, RS0
VIH VIL
VIH VIL
R/W
VIH tB tL tr VIH VIL tD VOH VOL tC Output Data tW tf VIH VIL tO
VIH tA
E
VIL
DB0 to DB7
VOH VOL
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* Serial Interface Mode
(VDD = 2.7 to 5.5 V, Ta = -40 to +85C) Parameter
SHT Cycle Time CS Setup Time CS Hold Time CS "H" Pulse Width SHT Setup Time SHT Hold Time SHT "H" Pulse Width SHT "L" Pulse Width SHT Rise Time SHT Fall Time
Symbol tSCY tCSU tCH tCSWH tSSU tSH tSWH tSWL tSR tSF tDISU tDIH tDOD tCDH
Min. 500 100 100 200 60 200 200 200 -- -- 100 100 -- 0
Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- --
Max. -- -- -- -- -- -- -- -- 50 50 -- -- 160 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Sl Setup Time Sl Hold Time Data Output Delay Time Data Output Hold Time
tSCY
CS
tCSWH VIL VIH tCH VIH VIH
VIH
VIL tSSU VIH tSWL tSR tSWH VIH tDIH VIH VIL tDOD VOH VIH tSF tSH VIH
tCSU
SHT
VIL tDISU VIH VIL tDOD
VIL
SI
tCDH VOH
SO
VOL
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FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER) These registers are selected by setting the level of the Register Selection input pins RS0 and RS1. The DR is selected when both RS0 and RS1 are "H". The IR is selected when RS0 is "L" and RS1 is "H". The ER is selected when both RS0 and RS1 are "L". (When RS0 is "H" and RS1 is "L", the ML9044A is not selected.) The IR stores an instruction code and sets the address code of the display data RAM (DDRAM) or the character generator RAM (CGRAM). The microcontroller (CPU) can write to the IR but cannot read from the IR. The ER stores a contrast adjusting code and sets the address code of the arbitrator RAM (ABRAM). The CPU can write to or read from the ER. The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read from the DDRAM, ABRAM and CGRAM. The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or CGRAM. When an address code is written in the IR or ER, the data of the specified address is automatically transferred from the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM and CGRAM can be checked by allowing the CPU to read the data stored in the DR. After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is selected to be ready for the next writing by the CPU. Similarly, after the CPU reads the data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is set in the DR to be ready for the next reading by the CPU. Writing in or reading from these 3 registers is controlled by changing the status of the R/W (Read/Write) pin. Table 1 R/W pin status and register operation
R/W L H L H L H L H RS0 L L H H L L H H RS1 H H H H L L L L Writing in the IR Reading the Busy flag (BF) and the address counter (ADC) Writing in the DR Reading from the DR Writing in the ER Reading the contrast code Disabled (Not in a busy state, not performing the writes) Disabled (Not in a busy state, not performing the reads. Note data read by the CPU is undefined since the data bus is high impedance.) Operation
Busy Flag (BF) The status "1" of the Busy Flag (BF) indicates that the ML9044A is carrying out internal operation. When the BF is "1", any new instruction is ignored. When R/W = "H", RS0 = "L" and RS1 = "H", the data in the BF is output to the DB7. New instructions should be input when the BF is "0". When the BF is "1", the output code of the address counter (ADC) is undefined.
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Address Counter (ADC) The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and also provides a cursor display address. When an instruction code specifying DDRAM, ABRAM or CGRAM address setting is input to the pre-defined register, the register selects the specified DDRAM, ABRAM or CGRAM and transfers the address code to the ADC. The address data in the ADC is automatically incremented (or decremented) by 1 after the display data is written in or read from the DDRAM, ABRAM or CGRAM. The data in the ADC is output to DB0 to DB6 when R/W = "H", RS0 = "L", RS1 = "H" and BF = "0". Timing Generator The timing generator generates timing signals for the internal operation of the ML9044A activated by the instruction sent from the CPU or for the operation of the internal circuits of the ML9044A such as DDRAM, ABRAM, CGRAM and CGROM. Timing signals are generated so that the internal operation carried out for LCD displaying will not be interfered by the internal operation initiated by accessing from the CPU. For example, when the CPU writes data in the DDRAM, the display of the LCD not corresponding to the written data is not affected.
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Display Data RAM (DDRAM) This RAM stores the 8-bit character codes (see Table 2). The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below. The DDRAM addresses (to be set in the ADC) are represented in hexadecimal.
DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADC
MSB
LSB Hexadecimal
Hexadecimal (Example) Representation of DDRAM address = 12 ADC 0 0 1 1 0
0 2
1
0
1) Relationship between DDRAM addresses and display positions (1-line display mode)
Digit 12 34 5 23 24 16 17 Right end Display position DD RAM address (hexadecimal)
00 01 02 03 04 Left end
In the 1-line display mode, the ML9044A can display up to 24 characters from digit 1 to digit 24. While the DDRAM has addresses "00" to "4F" for up to 80 character codes, the area not used for display can be used as a RAM area for general data. When the display is shifted by instruction, the relationship between the LCD display and the DDRAM address changes as shown below:
Digit 12
34
23 24 15 16
(Display shifted to the right) 4F 00 01 02
Digit 12
34
5
23 24 17 18
(Display shifted to the left) 01 02 03 04 05
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2) Relationship between DDRAM addresses and display positions (2-line display mode) In the 2-line mode, the ML9044A can display up to 48 characters (24 characters per line) from digit 1 to digit 24.
Digit 12345 Line 1 00 01 02 03 04 Line 2 40 41 42 43 44 23 24 16 17 56 57 Display position DD RAM address (hexadecimal)
Note: The DDRAM address at digit 24 in the first line is not consecutive to the DDRAM address at digit 1 in the second line. When the display is shifted by instruction, the relationship between the LCD display and the DDRAM address changes as shown below:
Digit 12345 Line 1 27 00 01 02 03 Line 2 67 40 41 42 43 Digit 12345 Line 1 01 02 03 04 05 Line 2 41 42 43 44 45 23 24 15 16 55 56
(Display shifted to the right)
(Display shifted to the left)
23 24 17 18 57 58
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Character Generator ROM (CGROM) The CGROM generates small character patterns (5 x 7 dots, 160 patterns) or large character patterns (5 x 10 dots, 32 patterns) from the 8-bit character code signals in the DDRAM. When the 8-bit character code corresponding to a character pattern in the CGROM is written in the DDRAM, the character pattern is displayed in the display position specified by the DDRAM address. Character codes 20 to 7F and A0 to FF are contained in the character code area in the CG ROM. Character codes 20 to 7F and A0 to DF are contained in the character code area for the 5 x 7-dot character patterns. Character codes E0 to FF are contained in the ROM area for 5 x 10-dot character patterns. The general character generator ROM codes are 51A/51B. The relationship between character codes and general purpose character patterns are indicated in Table 2.
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Character Generator RAM (CGRAM) The CGRAM is used to generate user-specific character patterns that are not in the CGROM. CGRAM (64 bytes = 512 bits) can store up to 8 small character patterns (5 x 8 dots) or up to 4 large character patterns (5 x 11 dots). When displaying a character pattern stored in the CGRAM, write an 8-bit character code (00 to 07 or 08 to 0F; hex.) assigned in Table 2 to the DDRAM. This enables outputting the character pattern to the LCD display position corresponding to the DDRAM address. The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address. The following describes how character patterns are written in and read from the CGRAM. 1) Small character patterns (5 x 8 dots) (See Table 3-1.) (1) A method of writing character patterns to the CGRAM from the CPU The three CGRAM address bit weights 0 to 2 select one of the lines constituting a character pattern. First, set the mode to increment or decrement from the CPU, and then input the CGRAM address. Write each line of the character pattern in the CGRAM through DB0 to DB7. The data lines DB0 to DB7 correspond to the CGRAM data bit weights 0 to 7, respectively (see Table 31). Input data "1" represents the ON status of an LCD dot and "0" represents the OFF status. Since the ADC is automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not necessary to set the CGRAM address again. The bottom line of a character pattern (the CGRAM address bit weights 0 to 2 are all "1", which means 7 in hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display the cursor. Whereas the data given by the CGRAM data bit weights 0 to 4 is output to the LCD as display data, the data given by the CGRAM data bit weights 5 to 7 is not. Therefore, the CGRAM data bit weights 5 to 7 can be used as a RAM area. (2) A method of displaying CGRAM character patterns on the LCD The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bit weight 3 of a character code is not used, the character pattern "0" in Table 3-1 can be selected using the character code "00" or "08" in hexadecimal. When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the DDRAM, the character pattern is displayed in the display position specified by the DDRAM address. (The DDRAM data bit weights 0 to 2 correspond to the CGRAM address bit weights 3 to 5, respectively.)
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2) Large character patterns (5 x 11 dots) (See Table 3-2.) (1) A method of writing character patterns to the CGRAM from the CPU The four CGRAM address bit weights 0 to 3 select one of the lines constituting a character pattern. First, set the mode to increment or decrement from the CPU, and then input the CGRAM address. Write each line of the character pattern code in the CGRAM through DB0 to DB7. The data lines DB0 to DB7 correspond to the CGRAM data bit weights 0 to 7, respectively (see Table 32). Input data "1" represents the ON status of an LCD dot and "0" represents the OFF status. Since the ADC is automatically incremented or decremented by 1 after the data is written to the CGRAM, it is not necessary to set the CGRAM address again. The bottom line of a character pattern (the CGRAM address bit weights 0 to 3 are all "1", which means A in hexadecimal) is a cursor line. The ON/OFF pattern of this line is ORed with the cursor pattern for displaying on the LCD. Therefore, the pattern data for the cursor position should be all zeros to display the cursor. Whereas CGRAM data bit weights 0 to 4 are output as display data to the LCD when CGRAM address bit weights 0 to 3 are "0" to "A" in hexadecimal, the data given by the CGRAM data bit weights 5 to 7 or the CGRAM addresses B to F in hexadecimal is not. These bits can be written and read as a RAM area. (2) A method of displaying CGRAM character patterns on the LCD The CGRAM is selected when the higher-order 4 bits of a character code are all zeros. Since bit weights 0 and 3 of a character code are not used, the character pattern "g" in Table 3-2 can be selected with a character code "02", "03", "0A" or "0B" in hexadecimal. When the 8-bit character code corresponding to a character pattern in the CGRAM is written to the DDRAM, the character pattern is displayed in the display position specified by the DDRAM address. (The DDRAM data bit weights 1 and 2 correspond to the CGRAM address bit weights 4 and 5, respectively.)
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Arbitrator RAM (ABRAM) The arbitrator RAM (ABRAM) stores arbitrator display data. 120 dots can be displayed in both 1-line and 2-line display modes. The arbitrator RAM has the addresses (hexadecimal) from "00" to "1F" and the valid display address area is from 00 to 23 (0H to 17H). The area of 24 to 31 (18H to 1FH) not used for display can be used as a data RAM area for general data. Even if the display is shifted by instruction, the arbitrator display is not shifted. A capacity of 8 bits by 32 addresses (= 256 bits) is available for data write. First set the mode to increment or decrement from the CPU, and then input the ABRAM address. Write Display-ON data in the ABRAM through DB0 to DB7. DB0 to DB7 correspond to the ABRAM data bit weights 0 to 7 respectively. Input data "1" represents the ON status of an LCD dot and "0" represents the OFF status. Since ADC is automatically incremented or decremented by 1 after the data is written to the ABRAM, it is not necessary to set the ABRAM address again. Whereas ABRAM data bit weights 0 to 4 are output as display data to the LCD, the ABRAM data bit weights 5 to 7 are not. These bits can be used as a RAM area. The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
DB6 DB5 DB4 DB3 DB2 DB1 DB0 ADC
MSB LSB
Hexadecimal
Hexadecimal
The arbitrator RAM can store a maximum of 120 dots of the arbitrator Display-ON data in units of 5 dots. The relationship with the LCD display positions is shown below.
Configuration of input display data Input data DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 * * * E4 E3 E2 E1 E0 Display - ON data E4 E0 Sn = ABRAM address (0 to 23) * Don't Care Relationship between display-ON data and segment pins 5XSn+1 5XSn+5
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Table 2
Relationship between Character Codes and Character Patterns of the ML9044A51A/51B (General Character Codes)
5x7-dot ROM area: 20H to 7FH, A0H to DFH 5x10-dot ROM area: E0H to FFH
The character code area in the CG ROM: Character codes 20H to 7FH, A0H to FFH.
The CG RAM area
00H: 08H: 20H:
: Character codes 00H to FFH
28H: ( 30H: 0 38H: 8 40H: @ 48H: H 50H: P
CG RAM(1) CG RAM(1)
01H:
09H:
21H: !
29H: )
31H: 1
39H: 9
41H: A
49H: I
51H: Q
CG RAM(2) CG RAM(2)
02H:
0AH:
22H: "
2AH: *
32H: 2
3AH: :
42H: B
4AH: J
52H: R
CG RAM(3) CG RAM(3)
03H:
0BH:
23H: #
2BH: +
33H: 3
3BH: ;
43H: C
4BH: K
53H: S
CG RAM(4) CG RAM(4)
04H:
0CH:
24H: $
2CH: ,
34H: 4
3CH: <
44H: D
4CH: L
54H: T
CG RAM(5) CG RAM(5)
05H:
0DH:
25H: %
2DH: -
35H: 5
3DH: =
45H: E
4DH: M
55H: U
CG RAM(6) CG RAM(6)
06H:
0EH:
26H: &
2EH: .
36H: 6
3EH: >
46H: F
4EH: N
56H: V
CG RAM(7) CG RAM(7)
07H:
0FH:
27H: '
2FH: /
37H: 7
3FH: ?
47H: G
4FH: O
57H: W
CG RAM(8) CG RAM(8)
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Table 3-1
Relationship between CGRAM address bits, CGRAM data bits (character pattern) and DDRAM data bits (character code) in 5 x 7 dot character mode. (Examples)
CG RAM CG RAM data DD RAM data address (Character pattern) (Character code) 5 4 3 2 1 0 76543210 76543210 MSB LSB MSB LSB MSB LSB 0 0 0 0 0 0 xxx 0 1 1 1 0 10001 001 10001 010 10001 011 100 10001 0000x000 10001 101 110 01110 111 00000 xxx 1 0 0 0 1 001000 10010 001 10100 010 11000 011 10100 0000x001 100 10010 101 110 10001 111 00000 1110 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 xxx 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0000x111
x: Don't Care
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Table 3-2
Relationship between CGRAM address bits, CGRAM data bits (character pattern) and DDRAM data bits (character code) in 5 x 10 dot character mode (Examples)
CG RAM address 543210 MSB LSB 000000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 010000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 110 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CG RAM data
(Character pattern)
DD RAM data
(Character code)
76543210 MSB LSB xxx 0 1 0 0 0 01111 10010 01111 01010 11111 00010 00000 00000 00000 00000 xxxxx
76543210 MSB LSB
0000x00x
xxx 0 0 0 0 0 00000 01111 10001 10001 10001 01111 00001 00001 01110 00000 xxxxx
0000x01x
0 xxx 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
00000 00000 11011 01010 10001 10001 01110 00000 00000 00000 00000 xxxxx
0000x11x
x: Don't Care
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Cursor/Blink Control Circuit This circuit generates the cursor and blink of the LCD. The operation of this circuit is controlled by the program of the CPU. The cursor/blink display is carried out in the position corresponding to the DDRAM address set in the ADC (Address Counter). For example, when the ADC stores a value of "07" (hexadecimal), the cursor or blink is displayed as follows:
DB6 ADC 0 00 0 Digit 12 In 1-line display mode 34 0 DB0 111 7 567 8 9 23 24 16 17
00 01 02 03 04 05 06 07 08
Cursor/blink position Digit 12 In 2-line display mode First line
34
567
8
9
23 24 16 17 56 57
00 01 02 03 04 05 06 07 08
Second line 40 41 42 43 44 45 46 47 48
Cursor/blink position
Note:
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC. Therefore, the cursor or blink display should be inhibited while the ADC is holding a CGRAM or ABRAM address.
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LCD Display Circuit (COM1 to COM17, SEG1 to SEG120, SSR and CSR) The ML9044A has 17 common signal outputs and 120 segment signal outputs to display 24 characters (in the 1line display mode) or 48 characters (in the 2-line display mode). The character pattern is converted into serial data and transferred in series through the shift register. The transfer direction of serial data is determined by the SSR pin. The shift direction of common signals is determined by the CSR pin. The following tables show the transfer and shift directions:
SSR L H CSR L L L L L L H H H H H H duty 1/9 1/9 1/12 1/12 1/17 1/17 1/9 1/9 1/12 1/12 1/17 1/17
Transfer direction SEG1 SEG120 SEG120 SEG1 AS bit L H L H L H L H L H L H Shift Direction COM1 COM9 COM1 COM9 COM1 COM12 COM1 COM12 COM1 COM17 COM1 COM17 COM9 COM1 COM9 COM1 COM12 COM1 COM12 COM1 COM17 COM1 COM17 COM1 Arbitrator's common pin COM9 COM1 COM12 COM1 COM17 COM1 COM1 COM9 COM1 COM12 COM1 COM17
* Refer to the Expansion Instruction Codes section about the AS bit. Signals to be input to the SSR and CSR pins should be determined at power-on and be kept unchanged.
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Built-in Reset Circuit The ML9044A is automatically initialized when the power is turned on. During initialization, the Busy Flag (BF) is "1" and the ML9044A does not accept any instruction from the CPU (other than the Read BF instruction). The Busy Flag is "1" for about 15 ms after the VDD becomes 2.7 V or higher. During this initialization, the ML9044A performs the following instructions: 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) Display clearing CPU interface data length = 8 bits 1-line LCD display Font size = 5 x 7 dots ADC counting = Increment Display shifting = None Display = Off Cursor = Off Blinking = Off Arbitrator = Displayed in the lower line Setting 1FH (hexadecimal) to the Contrast Data
(DL = "1") (N = "0") (F = "0") (I/D = "1") (S = "0") (D = "0") (C = "0") (B = "0") (AS = "0")
To use the built-in reset circuit, the power supply conditions shown below should be satisfied. Otherwise, the built-in reset circuit may not work properly. In such a case, initialize the ML9044A with the instructions from the CPU. The use of a battery always requires such initialization from the CPU. (See "Initial Setting of Instructions")
2.7 V
0.2 V tON 0.1 ms tON 100 ms
0.2 V tOFF 1 ms tOFF
0.2 V
Figure 1 Power-on and Power-off Waveform
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I/F with CPU Parallel interface mode The ML9044A can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any 8-bit or 4-bit microcontroller (CPU). 1) 8-bit interface data length The ML9044A uses all of the 8 data bus lines DB0 to DB7 at a time to transfer data to and from the CPU. 2) 4-bit interface data length The ML9044A uses only the higher-order 4 data bus lines DB4 to DB7 twice to transfer 8-bit data to and from the CPU. The ML9044A first transfers the higher-order 4 bits of 8-bit data (DB4 to DB7 in the case of 8-bit interface data length) and then the lower-order 4 bits of the data (DB0 to DB3 in the case of 8-bit interface data length). The lower-order 4 bits of data should always be transferred even when only the transfer of the higher-order 4 bits of data is required. (Example: Reading the Busy Flag) Two transfers of 4 bits of data complete the transfer of a set of 8-bit data. Therefore, when only one access is made, the following data transfer cannot be completed properly.
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RS1 RS0 R/W E Busy (Internal operation) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
IR7 IR6 IR5 IR4 IR3 IR2 IR1 IR0 Busy No Busy
ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
Writing In IR (Instruction Register)
Reading BF (Busy Flag) and ADC (Address Counter)
Writing In DR (Data Register)
Figure 2 8-Bit Data Transfer
RS1 RS0 R/W E Busy (Internal operation) DB7 DB6 DB5 DB4
IR7 IR6 IR5 IR4
IR3 IR2 IR1 IR0
Busy
No Busy
ADC6 ADC5 ADC4
ADC3 ADC2 ADC1 ADC0
DR7 DR6 DR5 DR4
DR3 DR2 DR1 DR0
Writing In IR (Instruction Register)
Reading BF (Busy Flag) and ADC (Address Counter)
Writing In DR (Data Register)
Figure 3 4-Bit Data Transfer
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Serial Interface Mode In the Serial I/F Mode, the ML9044A interfaces with the CPU via the CS, SHT, SI and SO pins. Writing and reading operations are executed in units of 16 bits after the CS signal falls down. If the CS signal rises up before the completion of 16-bit unit access, this access is ignored. When the BF bit is "1", the ML9044A cannot accept any other instructions. Before inputting a new instruction, check that the BF bit is "0". Any access when the BF bit is "1" is ignored. Data format is LSB-first. Examples of Access in the Serial I/F Mode
1) WRITE MODE CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
SHT BUSY (Internal operation) SI SO
1 1 1 1 1 R/W RS0 RS1 D0 D1 D2 D3 D4 D5 D6 D7 1
2) READ MODE CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
SHT BUSY (Internal operation) SI SO
1 1 1 1 1 R/W RS0 RS1 1
D0
D1
D2
D3
D4
D5
D6
D7
Note 1: Higher 5 bits of each instruction must be input at a "H" level. Note 2: Lower 8 bits are "don't care" when the instructions in the READ MODE are set. Note 3: After one instruction is input, the next instruction must be input after the CS pin is pulled at a "H" level.
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Instruction Codes Table of Instruction Codes
Code Instruction RS1 RS0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0 0 0 1 Function Execution Time f = 270 kHz
Display Clear
Cursor Home
1
0
0
0
0
0
0
0
0
1
X
Entry Mode Setting
1
0
0
0
0
0
0
0
1
I/D
S
Display 1 ON/OFF Control Cursor/Display Shift 1
0
0
0
0
0
0
1
D
C
B
0
0
0
0
0
1
S/C R/L
X
X
Function Setting 1 CGRAM Address Setting DDRAM Address Setting Busy Flag/ Address Read RAM Data Write
0
0
0
0
1
DL
N
F
X
X
1
0
0
0
1
ACG
1
0
0
1
ADD
1 1
0 1 1 0 0
1 0 1 0 0
BF
ADC WRITE DATA READ DATA
RAM Data Read 1 Arbitrator 0 Display Line Set Contrast Control 0 Data Write Contrast Control 0 Data Read
Clears all the displayed digits of the LCD and sets the DDRAM address 0 in 1.52 ms the address counter. The arbitrator data is cleared. Sets the DDRAM address 0 in the address counter and shifts the display 1.52 ms back to the original. The content of the DDRAM remains unchanged. Determines the direction of movement of the cursor and whether or not to shift 37 s the display. This instruction is executed when data is written or read. Sets LCD display ON/OFF (D), cursor ON/OFF or cursor-position character 37 s blinking ON/OFF. Moves the cursor or shifts the display 37 s without changing the content of the DDRAM. Sets the interface data length (DL), the 37 s number of display lines (N) or the type of character font (F). Sets on CGRAM address. After that, CGRAM data is transferred to and from 37 s the CPU. Sets a DDRAM address. After that, 37 s DDRAM data is transferred to and from the CPU. Reads the Busy Flag (indicating that 0 s the ML9044A is operating) and the content of the address counter. Writes data in DDRAM, ABRAM or 37 s CGRAM. Reads data from DDRAM, ABRAM or 37 s CGRAM. 37 s
0 0
0 0
0 1
0
0
0
1
AS Sets the arbitrator display line.
Writes data to control the contrast of 37 s the LCD. Reads data to control the contrast of 0 1 0 0 0 37 s the LCD. Sets an ABRAM address. After that, ABRAM 0 0 0 0 1 1 AAB 37 s ABRAM data is transferred to and from Address Setting the CPU. I/D = "1" (Increment) I/D = "0" (Decrement) The DD RAM: Display data RAM S = "1" (Shifts the display.) CG RAM: Character generator RAM execution S/C = "1" (Shifts display.) S/C = "0" (Moves the cursor.) time is ABRAM: Arbitrator data RAM R/L = "1" (Right shift) R/L = "0" (Left shift) dependent ACG: CGRAM address D/L = "1" (8-bit data) DL = "0" (4-bit data) upon ADD: DDRAM address N = "1" (2 lines) N = "0" (1 line) frequen(Corresponds to the cursor cies. F = "1" (5 x 10 dots) F = "0" (5 x 7 dots) address) -- BF = "1" (Busy) BF = "0" (Ready to accept an instruction) AAB: ABRAM address B = "1" (Enables blinking) ADC: Address counter (Used by C = "1" (Displays the cursor.) DDRAM, ABRAM and D = "1" (Displays a character pattern.) CGRAM) AS = "1" (Arbitrator Displays AS = "0" (Arbitrator Displays arbitrator on the arbitrator on the upper line) lower line) x: Don't Care
WRITE (Contrast Data) DATA READ (Contrast Data) DATA
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Instruction Codes An instruction code is a signal sent from the CPU to access the ML9044A. The ML9044A starts operation as instructed by the code received. The busy status of the ML9044A is rather longer than the cycle time of the CPU, since the internal processing of the ML9044A starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is "1"), the ML9044A cannot input the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is "0" before sending an instruction code to the ML9044A. 1) Display Clear
RS1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Instruction Code:
1
When this instruction is executed, the LCD display including arbitrator display is cleared and the I/D entry mode is set to "Increment". The value of "S" (Display shifting) remains unchanged. The position of the cursor or blink being displayed moves to the left end of the LCD (or the left end of the line 1 in the 2-line display mode). Note: All DDRAM and ABRAM data turn to "20" and "00" in hexadecimal, respectively. The value of the address counter (ADC) turns to the one corresponding to the address "00" (hexadecimal) of the DDRAM. The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
2) Cursor Home
RS1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0
Instruction code:
1
x
x: Don't Care
When this instruction is executed, the cursor or blink position moves to the left end of the LCD (or the left end of line 1 in the 2-line display mode). If the display has been shifted, the display returns to the original display position before shifting. Note: The value of the address counter (ADC) goes to the one corresponding to the address "00" (hexadecimal) of the DDRAM). The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency of 270 kHz.
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3) Entry Mode Setting
RS1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 S
Instruction code:
1
(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= "1"; increment) or to the left by 1 character position (I/D= "0"; decrement) after an 8-bit character code is written to or read from the DDRAM. At the same time, the address counter (ADC) is also incremented by 1 (when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement). After a character pattern is written to or read from the CGRAM, the address counter (ADC) is incremented by 1 (when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement). Also after data is written to or read from the ABRAM, the address counter (ADC) is incremented by 1 (when I/D = "1"; increment) or decremented by 1 (when I/D = "0"; decrement). (2) When S = "1", the cursor or blink stops and the entire display shifts to the left (I/D = "1") or to the right (I/D = "0") by 1 character position after a character code is written to the DDRAM. In the case of S = "1", when a character code is read from the DDRAM, when a character pattern is written to or read from the CGRAM or when data is written to or read from the ABRAM, normal read/write is carried out without shifting of the entire display. (The entire display does not shift, but the cursor or blink shifts to the right (I/D = "1") or to the left (I/D = "0") by 1 character position.) When S = "0", the display does not shift, but normal write/read is performed. Note: The execution time of this instruction is 37 s (maximum) at an oscillation frequency of 270 kHz.
4) Display ON/OFF Control
RS1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
Instruction code:
1
(1) The "D" bit (DB2) of this instruction determines whether or not to display character patterns on the LCD. When the "D" bit is "1", character patterns are displayed on the LCD. When the "D" bit is "0", character patterns are not displayed on the LCD and the cursor/blinking also disappear. Note: Unlike the Display Clear instruction, this instruction does not change the character code in the DDRAM and ABRAM.
(2) When the "C" bit (DB1) is "0", the cursor turns off. When both the "C" and "D" bits are "1", the cursor turns on. (3) When the "B" bit (DB0) is "0", blinking is canceled. When both the "B" and "D" bits are "1", blinking is performed. In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor are alternately displayed. Note: The execution time of this instruction is 37 s (maximum) at an oscillation frequency of 270 kHz.
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5) Cursor/Display Shift
RS1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 S/C DB2 R/L DB1 DB0
Instruction code:
1
x
x
x: Don't Care
S/C = "0", R/L = "0" S/C = "0", R/L = "1" S/C = "1", R/L = "0"
S/C = "1", R/L = "1"
This instruction shifts left the cursor and blink positions by 1 (decrements the content of the ADC by 1). This instruction shifts right the cursor and blink positions by 1 (increments the content of the ADC by 1). This instruction shifts left the entire display by 1 character position. The cursor and blink positions move to the left together with the entire display. The Arbitrator display is not shifted. (The content of the ADC remains unchanged.) This instruction shifts right the entire display by 1 character position. The cursor and blink positions move to the right together with the entire display. The Arbitrator display is not shifted. (The content of the ADC remains unchanged.)
In the 2-line mode, the cursor or blink moves from the first line to the second line when the cursor at digit 40 (27; hex) of the first line is shifted right. When the entire display is shifted, the character pattern, cursor or blink will not move between the lines (from line 1 to line 2 or vice versa). Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
6) Function Setting
RS1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 DL DB3 N DB2 F DB1 DB0
Instruction code:
1
x
x
x: Don't Care
(1) When the "DL" bit (DB4) of this instruction is "1", the data transfer to and from the CPU is performed once by the use of 8 bits DB7 to DB0. When the "DL" bit (DB4) of this instruction is "0", the data transfer to and from the CPU is performed twice by the use of 4 bits DB7 to DB4. (2) The 2-line display mode is selected when the "N" bit (DB3) of this instruction is "1". The 1-line display mode is selected when the "N" bit is "0". (3) The character font represented by 5 x 7 dots is selected when the "F" bit (DB2) of this instruction is "1". The character font represented by 5 x 10 dots is selected when the "F" bit is "1" and the "N" bit is "0". After the ML9044A is powered on, this function setting should be carried out before execution of any instruction except the Busy Flag Read. After this function setting, no instructions other than the DL Set instruction can be executed. In the Serial I/F Mode, DL setting is ignored.
N 0 0 1 1 F 0 1 0 1 Number of display lines 1 1 2 2 Font size 5x7 5 x 10 5x7 5x7 Duty 1/9 1/12 1/17 1/17 Number of biases 4 4 5 5 Number of common signals 9 12 17 17
Note:
The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
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7) CGRAM Address Setting
RS1 RS0 0 R/W 0 DB7 0 DB6 1 DB5 C5 DB4 C4 DB3 C3 DB2 C2 DB1 C1 DB0 C0
Instruction code:
1
This instruction sets the CGRAM address to the data represented by the bits C5 to C0 (binary). The CGRAM addresses are valid until DDRAM or ABRAM addresses are set. The CPU writes or reads character patterns starting from the one represented by the CGRAM address bits C5 to C0 set in the instruction code at that time. Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz. 8) DDRAM Address Setting
RS1 RS0 0 R/W 0 DB7 1 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0
Instruction code:
1
This instruction sets the DDRAM address to the data represented by the bits D6 to D0 (binary). The DDRAM addresses are valid until CGRAM or ABRAM addresses are set. The CPU writes or reads character codes starting from the one represented by the DDRAM address bits D6 to D0 set in the instruction code at that time. In the 1-line mode (the "N" bit is "0"), the DDRAM address represented by bits D6 to D0 (binary) should be in the range "00" to "4F" in hexadecimal. In the 2-line mode (the "N" bit is "1"), the DDRAM address represented by bits D6 to D0 (binary) should be in the range "00" to "27" or "40" to "67" in hexadecimal. If an address other than above is input, the ML9044A cannot properly write a character code in or read it from the DDRAM. Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz. 9) DDRAM/ABRAM/CGRAM Data Write
RS1 RS0 1 R/W 0 DB7 E7 DB6 E6 DB5 E5 DB4 E4 DB3 E3 DB2 E2 DB1 E1 DB0 E0
Instruction code:
1
A character code (E7 to E0) is written to the DDRAM, Display-ON data (E7 to E0) to the ABRAM or a character pattern (E7 to E0) to the CGRAM. The DDRAM, ABRAM or CGRAM is selected at the preceding address setting. After data is written, the address counter (ADC) is incremented or decremented as set by the Entry Mode Setting instruction (see 3). Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
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10) Busy Flag/Address Counter Read (Execution time: 0 s)
RS1 RS0 0 R/W 1 DB7 BF DB6 O6 DB5 O5 DB4 O4 DB3 O3 DB2 O2 DB1 O1 DB0 O0
Instruction code:
1
The "BF" bit (DB7) of this instruction tells whether the ML9044A is busy in internal operation (BF = "1") or not (BF = "0"). When the "BF" bit is "1", the ML9044A cannot accept any other instructions. Before inputting a new instruction, check that the "BF" bit is "0". When the "BF" bit is "0", the ML9044A outputs the correct value of the address counter. The value of the address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the DDRAM, ABRAM and CGRAM addresses is set in the counter is determined by the preceding address setting. When the "BF" bit is "1", the value of the address counter is not always correct because it may have been incremented or decremented by 1 during internal operation. 11) DDRAM/ABRAM/CGRAM Data Read
RS1 RS0 1 R/W 1 DB7 P7 DB6 P6 DB5 P5 DB4 P4 DB3 P3 DB2 P2 DB1 P1 DB0 P0
Instruction code:
1
A character code (P7 to P0) is read from the DDRAM, Display-ON data (P7 to P0) from the ABRAM or a character pattern (P7 to P0) from the CGRAM. The DDRAM, ABRAM or CGRAM is selected at the preceding address setting. After data is read, the address counter (ADC) is incremented or decremented as set by the Entry Mode Setting instruction (see 3). Note: Conditions for reading correct data (1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read instruction is input. (2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see 5) is input before this Data Read instruction is input. (3) When two or more consecutive RAM Data Read instructions are executed, the following read data is correct. Correct data is not output under conditions other than the cases (1), (2) and (3) above. Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
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Expansion Instruction Codes The busy status of the ML9044A is rather longer than the cycle time of the CPU, since the internal processing of the ML9044A starts at a timing which does not affect the display on the LCD. In the busy status (Busy Flag is "1"), the ML9044A executes the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is "0" before sending an expansion instruction code to the ML9044A. 1) Arbitrator Display Line Set
RS1 Expansion instruction code: 0 RS0 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 AS
This expansion instruction code sets the Arbitrator display line. The relationship between the status of this bit and the common outputs is as follows: For display examples, refer to LCD Drive Waveforms section.
CSR L L L L L L H H H H H H
duty 1/9 1/9 1/12 1/12 1/17 1/17 1/9 1/9 1/12 1/12 1/17 1/17
AS bit L H L H L H L H L H L H
Shift direction COM1COM9 COM1COM9 COM1COM12 COM1COM12 COM1COM17 COM1COM17 COM9COM1 COM9COM1 COM12COM1 COM12COM1 COM17COM1 COM17COM1
Arbitrator's common pin COM9 COM1 COM12 COM1 COM17 COM1 COM1 COM9 COM1 COM12 COM1 COM17
Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz. 2) Contrast Adjusting Data Write
RS1 Expansion instruction code: 0 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 F4 DB3 F3 DB2 F2 DB1 F1 DB0 F0
This instruction writes contrast adjusting data (F4 to F0) to the contrast register. After contrast adjusting data is written in the register, the potential (VLCD) output to the V5 pin varies according to the data written. The VLCD becomes maximum when the content of the contrast register is "1F" (hexadecimal) and becomes minimum when it is "00" (hexadecimal). Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
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3) Contrast Adjusting Data Read
RS1 Expansion instruction code: 0 RS0 0 R/W 1 DB7 0 DB6 0 DB5 0 DB4 G4 DB3 G3 DB2 G2 DB1 G1 DB0 G0
This instruction reads contrast adjusting data (G4 to G0) from the contrast register. Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz. 4) ABRAM Address Setting
RS1 Expansion instruction code: 0 RS0 0 R/W 1 DB7 0 DB6 1 DB5 1 DB4 H4 DB3 H3 DB2 H2 DB1 H1 DB0 H0
This instruction sets the ABRAM address to the data represented by the bits H4 to H0 (binary). The ABRAM addresses are valid until CGRAM or DDRAM addresses are set. The CPU writes or reads the Display-ON data starting from the one represented by the ABRAM address bits H4 to H0 set in the instruction code at that time. When the ABRAM address represented by bits H4 to H0 (binary) is in the range "00" to "17" in hexadecimal, data is output to the LCD as the arbitrator. Note: The execution time of this instruction is 37 s at an oscillation frequency (OSC) of 270 kHz.
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Examples of Combinations of ML9044A and LCD Panel (1) Driving the LCD of one 24-character line under the conditions of the 1-line display mode and the character font of 5 x 7 dots (1/9 duty, AS = "0", CSR = "L", SSR = "H")
COM1 Character COM8 COM9 Cursor Arbitrator
SEG120
SEG1
ML9044A
* COM10 to COM17 output Display-OFF common signals. (1/9 duty, AS = "1", CSR = "L", SSR = "H")
COM1 COM2
Arbitrator Character
COM9
Cursor
SEG120
SEG1
ML9044A
* COM10 to COM17 output Display-OFF common signals.
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(1/9 duty, AS = "0", CSR = "H", SSR = "L")
ML9044A
SEG1 SEG120
COM9 Character COM2 COM1
Cursor Arbitrator
* COM10 to COM17 output Display-OFF common signals. (1/9 duty, AS = "1", CSR = "H", SSR = "L")
ML9044A
SEG1 Arbitrator SEG120 COM9 COM8 Character Cursor COM1
* COM10 to COM17 output Display-OFF common signals.
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(2) Driving the LCD of one 24-character line under the conditions of the 1-line display mode and the character font of 5 x 10 dots (1/12 duty, AS = "0", CSR = "L", SSR = "H")
COM1 Character
COM11 COM12 SEG120 SEG1
Cursor Arbitrator
ML9044A
* COM13 to COM17 output Display-OFF common signals. (1/12 duty, AS = "1", CSR = "L", SSR = "H")
COM1 COM2 Arbitrator
Character COM12 Cursor
SEG120
SEG1
ML9044A
* COM13 to COM17 output Display-OFF common signals.
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(1/12 duty, AS = "0", CSR = "H", SSR = "L")
ML9044A
SEG1 SEG120
COM12 Character
Cursor Arbitrator
COM2 COM1
* COM13 to COM17 output Display-OFF common signals. (1/12 duty, AS = "1", CSR = "H", SSR = "L")
ML9044A
SEG1 SEG120
Arbitrator
COM12 COM11
Character
Cursor
COM1
* COM13 to COM17 output Display-OFF common signals.
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(3) Driving the LCD of two 24-character lines under the conditions of the 2-line display mode and the character font of 5 x 7 dots (1/17 duty, AS = "0", CSR = "L", SSR = "H")
COM1 Character COM8 COM9 Character COM16 COM17 Cursor Arbitrator Cursor
SEG120
SEG1
ML9044A
(1/17 duty, AS = "1", CSR = "L", SSR = "H")
COM1 COM2 Arbitrator Character COM9 COM10 Character COM17 Cursor Cursor
SEG120
SEG1
ML9044A
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(1/17 duty, AS = "0", CSR = "H", SSR = "L")
ML9044A
SEG1 SEG120
COM17 Character Cursor COM10 COM9 Character Cursor Arbitrator
COM2 COM1
(1/17 duty, AS = "1", CSR = "H", SSR = "L")
ML9044A
SEG1 SEG120
Arbitrator Character Cursor
COM17 COM16
COM9 COM8
Character Cursor COM1
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EXAMPLES OF VLCD GENERATION CIRCUITS
* With 1/4bias, a built-in contrast adjusting circuit and a voltage multiplier
VDD V1 V2 V3A V3B V4
ML9044A
V5 V5IN VC VCC VIN BE
Reference potential for voltage multiplier
* With 1/4 bias, a built-in contrast adjusting circuit and the V5 level input from an external circuit
* With 1/4 bias, no built-in contrast adjusting circuit and the V5 level input from an external circuit
VDD V1 V2 V3A V3B V4 V5 V5IN VC VCC VIN BE
VDD V1 V2 V3A V3B V4 V5 V5IN VC VCC VIN BE
ML9044A
ML9044A V5 level
V5 level
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* With 1/5 bias, a built-in contrast adjusting circuit and a voltage multiplier
VDD V1 V2 V3A V3B V4
ML9044A
V5 V5IN VC VCC VIN BE
Reference potential for voltage multiplier
* With 1/5 bias, a built-in contrast adjusting circuit and the V5 level input from an external circuit
* With 1/5 bias, no built-in contrast adjusting circuit and the V5 level input from an external circuit
VDD V1 V2 V3A V3B V4 V5 V5IN VC VCC VIN BE
VDD V1 V2 V3A V3B V4 V5 V5IN VC VCC VIN BE
ML9044A
ML9044A V5 level
V5 level
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LCD Drive Waveforms The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/9, 1/12 and 1/17 duties). See 1) to 3) below. The relationship between the duty ratio and the frame frequency is as follows:
Duty ratio 1/9 1/12 1/17 Frame Frequency 75.0 Hz 56.3 Hz 79.4 Hz
Note:
At an oscillation frequency (OSC) of 270 kHz
1) COM and SEG Waveforms on 1/9 Duty
CSR = "H" 2 1 9 8 7 6 *** 3 2 1 9 8 7 6 *** 3 2 1 9 8 COM1 (CSR = "L", AS = "L") COM2 (CSR = "L", AS = "H") COM9 (CSR = "H", AS = "L") COM8 (CSR = "H", AS = "H") (first character line) CSR = "L" 8 9 1 2 3 4 *** 7 8 9 1 2 3 4 *** 7 8 9 1 2 VDD V1 V2, V3B V4 V5 1 frame VDD V1 V2, V3B V4 V5
COM2 (CSR = "L", AS = "L") COM3 (CSR = "L", AS = "H") COM8 (CSR = "H", AS = "L") COM7 (CSR = "H", AS = "H") (second character line)
COM8 (CSR = "L", AS = "L") COM9 (CSR = "L", AS = "H") COM2 (CSR = "H", AS = "L") COM1 (CSR = "H", AS = "H") (cursor line)
VDD V1 V2, V3B V4 V5
COM9 (CSR = "L", AS = "L") COM1 (CSR = "L", AS = "H") COM1 (CSR = "H", AS = "L") COM9 (CSR = "H", AS = "H") (arbitrator line)
VDD V1 V2, V3B V4 V5
COM10 to COM17
VDD V1 V2, V3B V4 V5 Display turning-off waveform VDD V1 V2, V3B V4 V5 Display turning-on waveform
SEG
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2) COM and SEG Waveforms on 1/12 Duty
CSR = "H" 2 1 12 11 10 9 8 7 *** 4 3 2 1 12 11 10 9 8 7 *** COM1 (CSR = "L", AS = "L") COM2 (CSR = "L", AS = "H") COM12 (CSR = "H", AS = "L") COM11 (CSR = "H", AS = "H") (first character line) CSR = "L" 11 12 1 2 3 4 5 6 *** 9 10 11 12 1 2 3 4 5 6 *** VDD V1 V2, V3B V4 V5 1 frame VDD V1 V2, V3B V4 V5
COM2 (CSR = "L", AS = "L") COM3 (CSR = "L", AS = "H") COM11 (CSR = "H", AS = "L") COM10 (CSR = "H", AS = "H") (second character line)
COM11 (CSR = "L", AS = "L") COM12 (CSR = "L", AS = "H") COM2 (CSR = "H", AS = "L") COM1 (CSR = "H", AS = "H") (cursor line)
VDD V1 V2, V3B V4 V5
COM12 (CSR = "L", AS = "L") COM1 (CSR = "L", AS = "H") COM1 (CSR = "H", AS = "L") COM12 (CSR = "H", AS = "H") (arbitrator line)
VDD V1 V2, V3B V4 V5
COM13 to COM17
VDD V1 V2, V3B V4 V5 Display turning-off waveform VDD V1 V2, V3B V4 V5 Display turning-on waveform
SEG
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3) COM and SEG Waveforms on 1/17 Duty
CSR = "H" 2 1 17 16 15 14 13 12 11 10 9 8 7 6 5 *** 2 1 17 16 15 14 COM1 (CSR = "L", AS = "L") COM2 (CSR = "L", AS = "H") COM17 (CSR = "H", AS = "L") COM16 (CSR = "H", AS = "H") (first character line) CSR = "L" 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 *** 16 17 1 2 3 4 VDD V1 V2 V3A (V3B) V4 V5 1 frame
COM2 (CSR = "L", AS = "L") COM3 (CSR = "L", AS = "H") COM16 (CSR = "H", AS = "L") COM15 (CSR = "H", AS = "H") (second character line)
VDD V1 V2 V3A (V3B) V4 V5
COM16 (CSR = "L", AS = "L") COM17 (CSR = "L", AS = "H") COM2 (CSR = "H", AS = "L") COM1 (CSR = "H", AS = "H") (cursor line)
VDD V1 V2 V3A (V3B) V4 V5
COM17 (CSR = "L", AS = "L") COM1 (CSR = "L", AS = "H") COM1 (CSR = "H", AS = "L") COM17 (CSR = "H", AS = "H") (arbitrator line)
VDD V1 V2 V3A (V3B) V4 V5 Display turning-off waveform VDD V1 V2 V3A (V3B) V4 V5 Display turning-on waveform
SEG
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Initial Setting of Instructions (a) Data transfer from and to the CPU using 8 bits of DB0 to DB7 1) Turn on the power. 2) Wait for 15 ms or more after VDD has reached 2.7 V or higher. 3) Set "8 bits" with the Function Setting instruction. 4) Wait for 4.1 ms or more. 5) Set "8 bits" with the Function Setting instruction. 6) Wait for 100 s or more. 7) Set "8 bits" with the Function Setting instruction. 8) Check the Busy Flag for No Busy (or wait for 100 s or more). 9) Set "8 bits", "Number of LCD lines" and "Font size" with the Function Setting instruction. (After this, the number of LCD lines and the font size cannot be changed.) 10) Check the Busy Flag for No Busy. 11) Execute the Display ON/OFF Control Instruction, Display Clear Instruction, Entry Mode Setting instruction and Arbitrator Display Line Setting Instruction. 12) Check the Busy Flag for No Busy. 13) Initialization is completed. An example of instruction code for 3), 5) and 7)
RS1 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 x DB2 x DB1 x DB0 x
x: Don't Care
(b) Data transfer from and to the CPU using 4 bits of DB4 to DB7 1) Turn on the power. 2) Wait for 15 ms or more after VDD has reached 2.7 V or higher. 3) Set "8 bits" with the Function Setting instruction. 4) Wait for 4.1 ms or more. 5) Set "8 bits" with the Function Setting instruction. 6) Wait for 100 s or more. 7) Set "8 bits" with the Function Setting instruction. 8) Check the Busy Flag for No Busy (or wait for 100 s or longer). 9) Set "4 bits" with the Function Setting instruction. 10) Wait for 100 s or longer. 11) Set "4 bits", "Number of LCD lines" and "Font size" with the Function Setting instruction. (After this, the number of LCD lines and the font size cannot be changed.) 12) Check the Busy Flag for No Busy. 13) Execute the Display ON/OFF Control Instruction, Display Clear Instruction, Entry Mode Setting instruction and Arbitrator Display Line Setting Instruction. 14) Check the Busy Flag for No Busy. 15) Initialization is completed. An example of instruction code for 3), 5) and 7)
RS1 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1
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An example of instruction code for 9)
RS1 1 RS0 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 0
*: From 11), input data twice by the use of 4-bit data. *: In 13), check the Busy Flag for No Busy before executing each instruction. (c) Data transfer from and to the CPU using the serial I/F 1) Turn on the power. 2) Wait for 15 ms or more after VDD has reached 2.7 V or higher. 3) Check the busy flag for No Busy. 4) Set "Number of LCD lines" and "Font size" with the Function Setting Instruction.(After this, the number of LCD lines and the font size cannot be changed.) 5) Check the busy flag for No Busy. 6) Execute the Display ON/OFF Control Instruction, the Display Clear Instruction, the Entry Mode Instruction and the Arbitrator Display Line Setting Instruction. 7) Check the busy flag for No Busy. 8) Initialization is completed. *: In 6), check the Busy Flag for No Busy before executing each instruction.
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ML9044A-xxA CVWA PAD CONFIGURATION
Pad Layout Chip Size: Chip Thickness: Bump Size (1): Bump Size (2): 10.62 x 2.55 mm 62520 m 72 x 72 m (PAD No. 1-62, 183-189) 54 x 96 m (PAD No. 63-182)
Y
182 183
63 62 X
189 1 55
56
Pad Coordinates
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol V1 V2 V3A V3B V4 V5 V5IN VCC VC VlN BE VDD CSR SSR S/P VSS DB7 DB6 DB5 DB4 X (m) -5103 -4914 -4725 -4536 -4347 -4158 -3969 -3780 -3591 -3402 -3213 -3024 -2835 -2646 -2457 -2268 -2079 -1890 -1701 -1512 Y (m) -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 Pad 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol DB3 DB2 DB1 DB0 E R/W RS0 RS1 SO Sl SHT CS OSC2 OSCR OSC1 T3 T2 T1 COM1 COM2 X (m) -1323 -1134 -945 -756 -567 -378 -189 0 189 378 567 756 945 1134 1323 1512 1701 1890 2079 2268 Y (m) -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100
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Pad 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Symbol COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103
X (m) 2457 2646 2835 3024 3213 3402 3591 3780 3969 4158 4347 4536 4725 4914 5103 5184 5184 5184 5184 5184 5184 5184 4998 4914 4830 4746 4662 4578 4494 4410 4326 4242 4158 4074 3990 3906 3822 3738 3654 3570
Y (m) -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -720 -480 -240 0 240 480 720 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088
Pad 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Symbol SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63
X (m) 3486 3402 3318 3234 3150 3066 2982 2898 2814 2730 2646 2562 2478 2394 2310 2226 2142 2058 1974 1890 1806 1722 1638 1554 1470 1386 1302 1218 1134 1050 966 882 798 714 630 546 462 378 294 210
Y (m) 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088
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Pad 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155
Symbol SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28
X (m) 126 42 -42 -126 -210 -294 -378 -462 -546 -630 -714 -798 -882 -966 -1050 -1134 -1218 -1302 -1386 -1470 -1554 -1638 -1722 -1806 -1890 -1974 -2058 -2142 -2226 -2310 -2394 -2478 -2562 -2646 -2730
Y (m) 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088
Pad 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189
Symbol SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY
X (m) -2814 -2898 -2982 -3066 -3150 -3234 -3318 -3402 -3486 -3570 -3654 -3738 -3822 -3906 -3990 -4074 -4158 -4242 -4326 -4410 -4494 -4578 -4662 -4746 -4830 -4914 -4998 -5184 -5184 -5184 -5184 -5184 -5184 -5184
Y (m) 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 720 480 240 0 -240 -480 -720
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
ML9044A-xxACVWA ALIGNMENT MARK SPECIFICATION
Alignment Mark Coordinates
A Y ..................................................................................................... B
(0,0)
X C
Alignment Mark A B C
X (m) -5100 5100 5100
Y (m) 960 960 -840
Alignment Mark Layer Metal layers Alignment Mark Specification
Symbol Parameter Alignment Mark Width Alignment Mark Size Distance between Mark and Internal Pattern (MIN) Mark -- -- Mark A Mark B Mark C Mark A Size (m) 25.2 100.2 26.8 17.1 87.3 57.3 57.3 36.3 69.1 69.1 49.0
a b c
d
Distance between Mark and Adjacent Pad Metal Layer (MIN)
Mark B Mark C Mark A
e
Distance between Mark and Adjacent Pad Bump (MIN)
Mark B Mark C
Metal Bump
b d a c e Internal Pattern a
Metal Bump
b
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
ML9044A-xxB CVWA PAD CONFIGURATION
Pad Layout Chip Size: Chip Thickness: Bump Size (1): Bump Size (2): 10.62 x 2.55 mm 62520 m 72 x 72 m (PAD No. 1-55) 54 x 96 m (PAD No. 56-175)
175
Y
56
X
1
55
Pad Coordinates Note: The ML9044A-xxB does not have the dummy pads corresponding to the pad numbers 56 to 62 and 183 to 189 for the ML9044A-xxA.
Symbol V1 V2 V3A V3B V4 V5 V5IN VCC VC VlN BE VDD CSR SSR S/P VSS DB7 DB6 DB5 DB4 X (m) -5103 -4914 -4725 -4536 -4347 -4158 -3969 -3780 -3591 -3402 -3213 -3024 -2835 -2646 -2457 -2268 -2079 -1890 -1701 -1512 Y (m) -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 Pad 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol DB3 DB2 DB1 DB0 E R/W RS0 RS1 SO Sl X (m) -1323 -1134 -945 -756 -567 -378 -189 0 189 378 567 756 945 1134 1323 1512 1701 1890 2079 2268 Y (m) -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SHT CS
OSC2 OSCR OSC1 T3 T2 T1 COM1 COM2
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
Pad 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Symbol COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96
X (m) 2457 2646 2835 3024 3213 3402 3591 3780 3969 4158 4347 4536 4725 4914 5103 4998 4914 4830 4746 4662 4578 4494 4410 4326 4242 4158 4074 3990 3906 3822 3738 3654 3570 3486 3402 3318 3234 3150 3066 2982
Y (m) -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 -1100 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088
Pad 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Symbol SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56
X (m) 2898 2814 2730 2646 2562 2478 2394 2310 2226 2142 2058 1974 1890 1806 1722 1638 1554 1470 1386 1302 1218 1134 1050 966 882 798 714 630 546 462 378 294 210 126 42 -42 -126 -210 -294 -378
Y (m) 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
Pad 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148
Symbol SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28
X (m) -462 -546 -630 -714 -798 -882 -966 -1050 -1134 -1218 -1302 -1386 -1470 -1554 -1638 -1722 -1806 -1890 -1974 -2058 -2142 -2226 -2310 -2394 -2478 -2562 -2646 -2730
Y (m) 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088
Pad 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
Symbol SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
X (m) -2814 -2898 -2982 -3066 -3150 -3234 -3318 -3402 -3486 -3570 -3654 -3738 -3822 -3906 -3990 -4074 -4158 -4242 -4326 -4410 -4494 -4578 -4662 -4746 -4830 -4914 -4998
Y (m) 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088 1088
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
ML9044A-XXBCVWA ALIGNMENT MARK SPECIFICATION
Alignment Mark Coordinates
Y A .................................................................................................. B
(0,0)
X C
Alignment Mark A B C
X (m) -5100 5100 5100
Y (m) 960 960 -840
Alignment Mark Layer Metal layers Alignment Mark Specification
Symbol Parameter Alignment Mark Width Alignment Mark Size Distance between Mark and Internal Pattern (MIN) Mark -- -- Mark A Mark B Mark C Mark A Size (m) 25.2 100.2 26.8 17.1 87.3 57.3 57.3 164.7 69.1 69.1 173.7
a b c
d
Distance between Mark and Adjacent Pad Metal Layer (MIN)
Mark B Mark C Mark A
e
Distance between Mark and Adjacent Pad Bump (MIN)
Mark B Mark C
Metal Bump
b d a c e Internal Pattern a
Metal Bump
b
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
ML9044A-xxA/xxBCVWA GOLD BUMP SPECIFICATION
Gold Bump Specification
(Unit: m) MAX -- 59 101 35 77 77 122 2 20 4 5 --
Symbol A B C D E F G H I J K L
Parameter Bump Pitch (Min Section: Output Section) Bump Size (Output Section: Pitch Direction) Bump Size (Output Section: Depth Direction) Bump-to-Bump Distance (Output Section: Pitch Direction) Bump Size (Input Section: Pitch Direction) Bump Size (Input Section: Depth Direction) Bump-to-Bump Distance (Input Section: Pitch Direction) Sliding of Total Bump Pitches Bump Height Bump Height Dispersion Inside Chip (Range) Bump Edge Height Shear Strength (g) Bump Hardness (Hv: 25 g load)
MIN 84 49 91 25 67 67 112 -- 10 -- -- 30
TYP -- 54 96 30 72 72 117 -- 15 -- -- --
50 90 130 Chip Size; 10.62 mm x 2.55 mm Chip Thickness; 625 20 m
Top View and Cross Section View
A B*E
J C*F
Top View
D*F
Cross Section View
I
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
REVISION HISTORY
Document No.
PEDL9044A-01
Date
Dec. 2001
Page Previous Current Edition Edition
- 5 6 - 5 6
Description
Preliminary first edition Changed descriptions of Symbol BE. Changed descriptions of Symbols VC and VCC. Changed description of Symbol S/P. Added Symbol DUMMY and descriptions. Integrated Parameters " "H" Input Voltage 1" and " "H" Input Voltage 2", and Parameters " "L" Input Voltage 1" and " "L" Input Voltage 2". Changed Min. value of " "L" input voltage" from -0.3 to 0. Changed condition of Parameter "Input Current 2" from V1 = VDD to V1 = GND. Changed Note 6. Added Note. Added CS "H" pulse width. Changed timing diagrams. Added Note 3. Changed caption 4) from "Display Mode Setting" to "Display ON/OFF Control". Partially changed Section (1) of 4). Partially changed Section (3) of 6). Partially changed Section 8). Partially changed Section 11). Partially changed the content of Section "FEATURES". Changed a symbol in column "Applicable pin" from CS to CS. Partially changed Section (1) of 1). Partially changed Section (2). Partially changed Section "Arbitrator RAM (ABRAM)". Changed the figure for ADC. Partially changed Section 3). Partially changed Section 9). Partially changed Section 4). Partially changed Section 7) and Section 8). Partially changed Section 4). Partially added the content of Section 4) in (C).
8
8
10 PEDL9044A-02 Feb. 1, 2002 12 13 32 35 36 37 38 1 8 19 20 PEDL9044A-03 Feb. 6, 2002 21 27 35 37 40 37 PEDL9044A-04 Apr. 8, 2002 40 53
10 12 13 32 35 36 37 38 1 8 19 20 21 27 35 37 40 37 40 53
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PEDL9044A-04
OKI Semiconductor
ML9044A-xxA/xxB
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
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